Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/99867
Title: A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes
Authors: Hosseini, S. M. Ehsan
Chan, Kheong Sann
Goh, Wang Ling
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
Issue Date: 2008
Source: Hosseini, S. M. E., Chan, K. S., & Goh, W. L. (2008). A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes. 2nd International Conference on Signals, Circuits and Systems: Hammamet,Tunisia, (pp.1-6).
Abstract: This paper describes the implementation of a general and embedded decoder for the evaluation of unstructured low-density parity-check (LDPC) codes over additive-white Gaussian noise (AWGN) channels. The decoder, which has a serial architecture and moderate throughput, is a peripheral connected to the embedded PowerPC processor of a Xilinx Virtex-II Pro FPGA and is managed by the processor. This method of Hardware/ Software implementation provides the maximum flexibility for the development and rapid prototyping of the hardware-based simulator system. The decoding algorithm proposed in this paper belongs to the class of min-sum with correction factor in which the correction factor updates with the log-likelihood ratio (LLR) values.
URI: https://hdl.handle.net/10356/99867
http://hdl.handle.net/10220/6373
DOI: http://dx.doi.org/10.1109/ICSCS.2008.4746952
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Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Conference Papers

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