dc.contributor.authorChang, Richard Weng Yew
dc.contributor.authorSee, Kye Yak
dc.contributor.authorSoh, Wei-Shan
dc.contributor.authorOswal, Manish
dc.contributor.authorWang, Lin Biao
dc.date.accessioned2010-08-31T02:47:18Z
dc.date.available2010-08-31T02:47:18Z
dc.date.copyright2009en_US
dc.date.issued2009
dc.identifier.citationChang, R. W. Y., See, K. Y., Soh, W. S., Oswal, M., & Wang, L. B. (2009). High-speed signal termination analysis using a co-simulation approach. In proceedings of the 12th International Symposium on Integrated Circuits: Singapore, (pp.623-626).
dc.identifier.urihttp://hdl.handle.net/10220/6375
dc.description.abstractMatched terminations of high-speed digital buses have long been the focus of high-speed board design. With increasing edge rates, proper bus termination has become even more crucial in today’s high-speed PCB interconnect design. Using a co-simulation approach, the 3D electromagnetic (EM) effects of high-speed interconnects and the circuit behavioral IBIS models of active devices are combined to investigate highspeed clock termination designs. Such an approach allows the high-frequency effects to be taken into account and therefore yields good accuracy for realistic high-speed board. A practical example is demonstrated based on the co-simulation approach.en_US
dc.format.extent4 p.en_US
dc.language.isoenen_US
dc.rights© 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.en_US
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic systems::Signal processing
dc.titleHigh-speed signal termination analysis using a co-simulation approachen_US
dc.typeConference Paper
dc.contributor.conferenceIEEE International Symposium on Integrated Circuits (12th : 2009 : Singapore)en_US
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen_US
dc.identifier.openurlhttp://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5403694
dc.description.versionPublished versionen_US
dc.contributor.organizationGuided Systems Division, DSO National Laboratoriesen_US


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