Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/91031
Title: Impacts of bends and ground return vias on interconnects for high speed GHz designs
Authors: Chang, Richard Weng Yew
See, Kye Yak
Tan, Yang Long
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic packaging
Issue Date: 2008
Source: Chang, R. W. Y., See, K. Y., & Tan, Y. L. (2008). Impacts of bends and ground return vias on interconnects for high speed GHz designs. In proceedings of the Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility: Singapore, (pp.502-505).
Abstract: In the past only critical clock circuits are running at high speed but this is no longer true in today high-speed digital design world. Most of the digital traces on board are running at speed in excess of 200 MHz and drivers output with rise time less than 1 ns. Due to constraints of board size and highly complex designs, trace bends and inter-layer transitions through vias are unavoidable. This paper carries out a comprehensive study on the impacts of bends and ground return vias optimisation on signal integrity performance using a full-wave electromagnetic simulator. (CST Microwave Studio). This study will provide high-speed digital designers an in-depth assessment of these effects in high-speed GHz applications so that some design guides to avoid these effects can be established.
URI: https://hdl.handle.net/10356/91031
http://hdl.handle.net/10220/6386
DOI: 10.1109/APEMC.2008.4559922
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Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Conference Papers

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