Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/90762
Title: Memory characteristics of MOSFETs with densely stacked silicon nanocrystal layers in the gate oxide synthesized by low-energy ion beam
Authors: Ng, Chi Yung
Chen, Tupei
Ding, Liang
Fung, Stevenson Hon Yuen
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2006
Source: Ng, C. Y., Chen, T. P., Ding, L., & Fung, S. H. Y. (2006). Memory characteristics of MOSFETs with densely stacked silicon nanocrystal layers in the gate oxide synthesized by low-energy ion beam. IEEE Electron Device Letters, 27(4), 231-233.
Series/Report no.: IEEE electron device letters
Abstract: Densely stacked silicon nanocrystal layers embedded in the gate oxide of MOSFETs are synthesized with Si ion implantation into an SiO2 layer at an implantation energy of 2 keV. In this letter, the memory characteristics of MOSFETs with 7-nm tunnel oxide and 20-nm control oxide at various temperatures have been investigated. A threshold voltage window of ∼ 0.5 V is achieved under write/erase (W/E) voltages of +12 V/-12 V for 1 ms. The devices exhibit good endurance up to 105 W/E cycles even at a high operation temperature of 150°C. They also have good retention characteristics with an extrapolated ten-year memory window of ∼ 0.3 V at 100°C.
URI: https://hdl.handle.net/10356/90762
http://hdl.handle.net/10220/6413
ISSN: 0741-3106
DOI: 10.1109/LED.2006.871183
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Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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