dc.contributor.authorMeher, Pramod Kumar
dc.contributor.authorSrikanthan, Thambipillai
dc.contributor.authorPatra, Jagdish Chandra
dc.date.accessioned2011-09-21T06:41:59Z
dc.date.available2011-09-21T06:41:59Z
dc.date.copyright2006en_US
dc.date.issued2006
dc.identifier.citationMeher, P. K., Srikanthan, T., & Patra, J. C. (2006). Scalable and modular memory-based systolic architectures for discrete Hartley transform. IEEE Transactions on Circuits and Systems I: Regular Papers, 53(5), 1065-1077.en_US
dc.identifier.issn1549-8328en_US
dc.identifier.urihttp://hdl.handle.net/10220/7091
dc.description.abstractIn this paper, we present a design framework for scalable memory-based implementation of the discrete Hartley transform (DHT) using simple and efficient systolic and systolic-like structures for short and prime transform lengths, as well as, for lengths 4 and 8. We have used the proposed short-length structures to construct highly modular architectures for higher transform lengths by a new prime-factor implementation approach. The structures proposed for the prime-factor DHT, interestingly, do not involve any transposition hardware/time. Besides, it is shown here that an N-point DHT can be computed efficiently from two (N/2)-point DHTs of its even- and odd-indexed input subsequences in a recursive manner using a ROM-based multiplication stage. Apart from flexibility of implementation, the proposed structures offer significantly lower area-time complexity compared with the existing structures. The proposed schemes of computation of the DHT can conveniently be scaled not only for higher transform lengths but also according to the hardware constraint or the throughput requirement of the application.en_US
dc.format.extent13 p.en_US
dc.language.isoenen_US
dc.relation.ispartofseriesIEEE transactions on circuits and systems I: regular papersen_US
dc.rights© 2006 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [DOI: http://dx.doi.org/10.1109/TCSI.2006.870225].en_US
dc.subjectDRNTU::Engineering::Computer science and engineering::Computer systems organization::Processor architectures
dc.titleScalable and modular memory-based systolic architectures for discrete Hartley transformen_US
dc.typeJournal Article
dc.contributor.schoolSchool of Computer Engineeringen_US
dc.identifier.doihttp://dx.doi.org/10.1109/TCSI.2006.870225
dc.description.versionAccepted versionen_US
dc.identifier.rims125993


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