Concurrent error detection in bit-serial normal basis multiplication over GF(2^m) using multiple parity prediction schemes
Lee, Chiou Yng
Meher, Pramod Kumar
Patra, Jagdish Chandra
Date of Issue2010
School of Computer Engineering
New bit-serial architectures with concurrent error detection capability are presented to detect erroneous outputs in bit-serial normal basis multipliers over GF(2^m) using single and multiple-parity prediction schemes. It is shown that different types of normal basis multipliers could be realized by similar architectures. The proposed architectures can detect errors with nearly 100% probability.
DRNTU::Engineering::Computer science and engineering::Computer systems organization::Computer-communication networks
IEEE transactions on very large scale integration (VLSI) systems
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