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Title: Fast timing analysis of clock networks considering environmental uncertainty
Authors: Wang, Hai
Yu, Hao
Tan, Sheldon X. D.
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2012
Source: Wang, H., Yu, H., & Tan, S. X. D. (2012). Fast timing analysis of clock networks considering environmental uncertainty. Integration, the VLSI Journal, 45(4), 376-387.
Series/Report no.: Integration, the VLSI journal
Abstract: Dynamic power management can significantly introduce environmental uncertainties such as non-uniform temperature gradients and supply voltage fluctuations. This can bring many challenges for the system-level timing verification such as for global clock networks. This paper presents a fast verification of clock-skew by an incremental-SVD-based compact modeling assisted with adaptive sampling. Firstly, an incremental-SVD is developed to perform an efficient update of environmental uncertainties avoiding a repeated full SVD. Secondly, an adaptive sampling is presented to build accurate models to sample clock and clock-skew for generating macromodels in a wide frequency range. Experiments on a number of clock networks show that when compared to the traditional fast TBR method, our macromodeling by incremental-SVD and adaptive sampling can significantly reduce the runtime with a similar accuracy. In addition, when compared to the Krylov-subspace-based method, our macromodeling further reduces the waveform error with a similar runtime.
ISSN: 0167-9260
DOI: 10.1016/j.vlsi.2011.03.001
Rights: © 2011 Elsevier. This is the author created version of a work that has been peer reviewed and accepted for publication by Integration, the VLSI journal, Elsevier. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at:
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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