dc.contributor.authorHeryanto, A.
dc.contributor.authorPutra, W. N.
dc.contributor.authorTrigg, Alastair David
dc.contributor.authorGao, S.
dc.contributor.authorKwon, W. S.
dc.contributor.authorChe, Faxing
dc.contributor.authorAng, X. F.
dc.contributor.authorWei, J.
dc.contributor.authorMade, Riko I.
dc.contributor.authorGan, Chee Lip
dc.contributor.authorPey, Kin Leong
dc.date.accessioned2012-10-03T07:13:45Z
dc.date.available2012-10-03T07:13:45Z
dc.date.copyright2012en_US
dc.date.issued2012
dc.identifier.citationHeryanto, A., Putra, W. N., Trigg, A. D., Gao, S., Kwon, W. S., Che, F., et al. (2012). Effect of copper TSV annealing on via protrusion for TSV wafer fabrication. Journal of electronic materials, 41(9), 2533-2542.en_US
dc.identifier.issn0361-5235en_US
dc.identifier.urihttp://hdl.handle.net/10220/8698
dc.description.abstractThree-dimensional (3D) integrated circuit (IC) technologies are receiving increasing attention due to their capability to enhance microchip function and performance. While current efforts are focused on the 3D process development, adequate reliability of copper (Cu) through-silicon vias (TSVs) is essential for commercial high-volume manufacturing. Annealing a silicon device with copper TSVs causes high stresses in the copper and may cause a “pumping” phenomenon in which copper is forced out of the blind TSV to form a protrusion. This is a potential threat to the back-end interconnect structure, particularly for low-κ materials, since it can lead to cracking or delamination. In this work, we studied the phenomenon of Cu protrusion and microstructural changes during thermal annealing of a TSV wafer. The extruded Cu-TSV was observed using scanning electron microscopy (SEM), 3D profilometry, and atomic force microscopy (AFM). The electron backscatter diffraction (EBSD) technique was employed to study the grain orientation of Cu-TSV and evolution of the grain size as a function of annealing temperature. The elastic modulus and yield stress of copper were characterized using nanoindentation. A model for Cu protrusion is proposed to provide insight into the failure mechanism. The results help to solve a key TSV-related manufacturing yield and reliability challenge by enabling high-throughput TSV fabrication for 3D IC integration.en_US
dc.language.isoenen_US
dc.relation.ispartofseriesJournal of electronic materialsen_US
dc.rights© 2012 TMS.en_US
dc.subjectDRNTU::Engineering::Materials
dc.titleEffect of copper TSV annealing on via protrusion for TSV wafer fabricationen_US
dc.typeJournal Article
dc.contributor.schoolSchool of Materials Science and Engineeringen_US
dc.contributor.schoolSchool of Electrical and Electronic Engineering
dc.identifier.doihttp://dx.doi.org/10.1007/s11664-012-2117-3
dc.identifier.rims166545


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