An efficient channel clustering and flow rate allocation algorithm for non-uniform microfluidic cooling of 3D integrated circuits
Chang, Chip Hong
Date of Issue2013
School of Electrical and Electronic Engineering
Heat removal problem has been a bane of three dimensional integrated circuits (3DICs). Comparing with other passive cooling techniques, microfluidic cooling appears to be an ideal cooling solution due to its high thermal conductivity and scalability. Without regarding to the fact of non-uniform power distribution of integrated circuits, existing microfluidic cooling with uniform cooling effort incurs large thermal gradient and wastes pump power. This can be avoided by the customized non-uniform cooling scheme proposed in this paper. The microfluidic channels are divided into clusters of relatively homogeneous power distribution and an appropriate flow rate setting is applied to each cluster based on the total flow rate and the maximum allowable temperature of the 3DIC. This paper proposes an efficient clustering algorithm to guide the division of microchannels into clusters and the allocation of cooling resources to each cluster in order to achieve an effective microfluidic cooling with minimal total flow rate. A compact steady state thermal simulator has been developed and verified. Supported by this fast and accurate thermal model, the proposed cooling method and clustering algorithm have been applied to a 3D multi-core testbench for simulation. Compared to the uniform flow rate cooling, the maximum temperature and thermal gradient were reduced under the same total flow rate settings. On the other hand, for a specific peak temperature constraint, up to 21.8% saving in total flow rate with moderate thermal gradients is achieved by the proposed clustered microfluidic cooling.
DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Integration, the VLSI Journal
© 2011 Elsevier B.V. This is the author created version of a work that has been peer reviewed and accepted for publication by Integration, the VLSI journal, Elsevier B.V.. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at [DOI: http://dx.doi.org/10.1016/j.vlsi.2011.12.005].