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Title: Low power implantable neural recording front-end
Authors: Do, Anh Tuan
Tan, Yung Sern
Lam, Chun Kit
Je, Minkyu
Yeo, Kiat Seng
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2012
Source: Do, A. T., Tan, Y. S., Lam, C. K., Je, M., & Yeo, K. S. (2012). Low power implantable neural recording front-end. 2012 International SoC Design Conference (ISOCC 2012).
Abstract: Low power smart electronic designs for neural recording applications have recently become a major research topic in circuits and system society. Challenged by the complicated nature of the biology-electronic interface, implantable neural recording circuits must offer high quality signal acquisition while consuming as little power as possible. Furthermore, many applications demand on-chip smart features to maximize energy efficiency as well as to assist the subsequent software-based digital signal processing. This paper reviews the recent advancements in the field, followed by a proposed ultra low-power recording front-end. The proposed design consists of an adjustable gain and bandwidth low-noise amplifier, a bandpass filter, a unity gain buffer and a 9-bit ADC. When simulated using a 0.18 μm/1 V CMOS process, the whole channel consumes only 2.76 μW.
DOI: 10.1109/ISOCC.2012.6407122
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Conference Papers

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