Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/100815
Title: Detecting hardware trojan through time domain constrained estimator based unified subspace technique
Authors: Xue, Mingfu
Liu, Wei
Hu, Aiqun
Wang, Youdong
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
Issue Date: 2014
Source: XUE, M., LIU, W., HU, A., & WANG, Y. (2014). Detecting Hardware Trojan through Time Domain Constrained Estimator Based Unified Subspace Technique. IEICE Transactions on Information and Systems, E97.D(3), 606-609.
Series/Report no.: IEICE transactions on information and systems
Abstract: Hardware Trojan (HT) has emerged as an impending security threat to hardware systems. However, conventional functional tests fail to detect HT since Trojans are triggered by rare events. Most of the existing side-channel based HT detection techniques just simply compare and analyze circuit's parameters and offer no signal calibration or error correction properties, so they suffer from the challenge and interference of large process variations (PV) and noises in modern nanotechnology which can completely mask Trojan's contribution to the circuit. This paper presents a novel HT detection method based on subspace technique which can detect tiny HT characteristics under large PV and noises. First, we formulate the HT detection problem as a weak signal detection problem, and then we model it as a feature extraction model. After that, we propose a novel subspace HT detection technique based on time domain constrained estimator. It is proved that we can distinguish the weak HT from variations and noises through particular subspace projections and reconstructed clean signal analysis. The reconstructed clean signal of the proposed algorithm can also be used for accurate parameter estimation of circuits, e.g. power estimation. The proposed technique is a general method for related HT detection schemes to eliminate noises and PV. Both simulations on benchmarks and hardware implementation validations on FPGA boards show the effectiveness and high sensitivity of the new HT detection technique.
URI: https://hdl.handle.net/10356/100815
http://hdl.handle.net/10220/19687
ISSN: 0916-8532
DOI: 10.1587/transinf.E97.D.606
Rights: © 2014 The Institute of Electronics, Information and Communication Engineers. This paper was published in IEICE Transactions on Information and Systems and is made available as an electronic reprint (preprint) with permission of The Institute of Electronics, Information and Communication Engineers. The paper can be found at the following official DOI: http://dx.doi.org/10.1587/transinf.E97.D.606.  One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper is prohibited and is subject to penalties under law.
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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