Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/100928
Title: A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM
Authors: Cho, Uk Rae
Kim, Tony Tae-Hyoung
Yoon, Yong-Jin
Lee, Jong Cheol
Bae, Dae Gi
Kim, Nam Seog
Kim, Kang Young
Son, Young Jae
Yang, Jeong Suk
Sohn, Kwon Il
Kim, Sung Tae
Lee, In Yeol
Lee, Kwang Jin
Kang, Tae Gyoung
Kim, Su Chul
Ahn, Kee Sik
Byun, Hyun Geun
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2003
Source: Cho, U. R., Kim, T. H., Yoon, Y. J., Lee, J. C., Bae, D. G., Kim, N. S., et al. (2003). A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM. IEEE Journal of Solid State Circuits, 38(11), 1943-1951.
Series/Report no.: IEEE journal of solid state circuits
Abstract: A 1.2-V 72-Mb double data rate 3 (DDR3) SRAM achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits [5]. Single-ended main data lines halve the data line precharging power dissipation and the number of data lines. Clocks phase shifted by 0 , 90 , and 270 are generated through the proposed clock adjustment circuits. The proposed clock adjustment circuits make input data sampled with optimized setup/hold window. On-chip input termination with the linearity error of 4.1% is developed to improve signal integrity at higher data rates. A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM is fabricated in a 0.10- m CMOS process with five metals. The cell size and the chip size are 0.845 m2 and 151.1 mm2, respectively.
URI: https://hdl.handle.net/10356/100928
http://hdl.handle.net/10220/6438
ISSN: 0018-9200
DOI: 10.1109/JSSC.2003.818137
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Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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