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Title: An improved inverter-based readout scheme for low-power ISFET sensing array
Authors: Do, Anh Tuan
Je, Minkyu
Yeo, Kiat Seng
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2013
Source: Do, A. T., Je, M., & Yeo, K. S. (2013). An improved inverter-based readout scheme for low-power ISFET sensing array. Electronics letters, 49(24), 1517–1518.
Series/Report no.: Electronics letters
Abstract: Digital read-out scheme in ISFET sensing array is more advantageous when compared to the analog counterpart because of its lower power consumption, less area and less susceptible to environmental noise and parasitic. This work proposes an improved readout scheme in which each ISFET is stacked with a CMOS inverter to form a pH-to-time converter. pH level of the solution regulates the strength of the ISFET, which in turn modulates the delay of the stacked inverter and hence the pulse-width of the output signal. Simulation results using 0.18 μm/2.5V CMOS process show that the modulated pulse width changes linearly over a wide range of pH. Our design achieves 5 orders of magnitude smaller leakage, 40% lower dynamic power consumption while requires only 50% of silicon area when compared to the conventional design. It is therefore more suitable for large ISFET array implemented in nanoscale CMOS technologies.
ISSN: 1350-911X
DOI: 10.1049/el.2013.3025
Rights: © 2013 IET. This is the author created version of a work that has been peer reviewed and accepted for publication by Electronics Letters, IET. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at:
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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