An improved inverter-based readout scheme for low-power ISFET sensing array

Abstract

Digital read-out scheme in ISFET sensing array is more advantageous when compared to the analog counterpart because of its lower power consumption, less area and less susceptible to environmental noise and parasitic. This work proposes an improved readout scheme in which each ISFET is stacked with a CMOS inverter to form a pH-to-time converter. pH level of the solution regulates the strength of the ISFET, which in turn modulates the delay of the stacked inverter and hence the pulse-width of the output signal. Simulation results using 0.18 μm/2.5V CMOS process show that the modulated pulse width changes linearly over a wide range of pH. Our design achieves 5 orders of magnitude smaller leakage, 40% lower dynamic power consumption while requires only 50% of silicon area when compared to the conventional design. It is therefore more suitable for large ISFET array implemented in nanoscale CMOS technologies.