Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/101001
Title: A FVF based output capacitorless LDO regulator with wide load capacitance range
Authors: Chong, Sau Siong
Chan, Pak Kwong
Koay, K. C.
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2013
Source: Koay, K. C., Chong, S. S., & Chan, P. K. (2013). A FVF based output capacitorless LDO regulator with wide load capacitance range. 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), pp1488-1491.
Abstract: An output capacitorless low-dropout (LDO) regulator, which applies the proposed Dual Summed Miller Frequency Compensation (DSMFC) on Flipped Voltage Follower (FVF) structure with composite power transistor, is proposed. Validated by UMC 65nm CMOS process, the simulation results have shown that the proposed LDO regulator consumes only 13.2μA at a 1.2V supply, with a dropout voltage of 200mV. At a total of 10pF compensation capacitance, it can support 0-50mA load current for a load capacitance range of 10pF-100nF at typical process and temperature whilst 10pF-10nF at worst condition. The proposed LDO regulator is able to recover in 0.925μs at CL=50pF. The comparison results have shown that the maximum load capacitance is more than two orders of magnitude with respect to those of the FVF LDO counterparts at identical process, supply, quiescent power and compensation capacitance.
URI: https://hdl.handle.net/10356/101001
http://hdl.handle.net/10220/16695
DOI: 10.1109/ISCAS.2013.6572139
Rights: © 2013 IEEE
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Conference Papers

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