Please use this identifier to cite or link to this item:
https://hdl.handle.net/10356/101191
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Xiao, Zhe | en |
dc.contributor.author | Luo, Xianshu | en |
dc.contributor.author | Liow, Tsung-Yang | en |
dc.contributor.author | Lim, Peng Huei | en |
dc.contributor.author | Prabhathan, Patinharekandy | en |
dc.contributor.author | Zhang, Jing | en |
dc.contributor.author | Luan, Feng | en |
dc.date.accessioned | 2013-12-17T09:09:48Z | en |
dc.date.accessioned | 2019-12-06T20:35:01Z | - |
dc.date.available | 2013-12-17T09:09:48Z | en |
dc.date.available | 2019-12-06T20:35:01Z | - |
dc.date.copyright | 2013 | en |
dc.date.issued | 2013 | en |
dc.identifier.citation | Xiao, Z., Luo, X., Liow, T.-Y., Lim, P. H., Prabhathan, P., Zhang, J., et al. (2013). Design and characterization of low loss 50 picoseconds delay line on SOI platform. Optics express, 21(18), 21285-21292. | en |
dc.identifier.issn | 1094-4087 | en |
dc.identifier.uri | https://hdl.handle.net/10356/101191 | - |
dc.description.abstract | We design and experimentally demonstrate 50 picoseconds (ps) low loss delay line on 300 nm SOI platform. The delay line unit consists of straight rib waveguide and strip bend section linked by a transition taper waveguide. Low propagation loss of ~0.1 dB/cm is achieved on the straight rib waveguide. With taking into account both low loss and desirable delay, a complete design and characterization process for passive delay line is presented. Our measurement results show that about 0.7 dB excess loss is achievable for 50 ps delay. The loss can be further reduced by adjusting the layout parameters. | en |
dc.description.sponsorship | ASTAR (Agency for Sci., Tech. and Research, S’pore) | en |
dc.language.iso | en | en |
dc.relation.ispartofseries | Optics express | en |
dc.rights | © 2013 Optical Society of America. | en |
dc.subject | DRNTU::Engineering::Electrical and electronic engineering::Optics, optoelectronics, photonics | en |
dc.title | Design and characterization of low loss 50 picoseconds delay line on SOI platform | en |
dc.type | Journal Article | en |
dc.contributor.school | School of Electrical and Electronic Engineering | en |
dc.contributor.research | Research Techno Plaza | en |
dc.identifier.doi | 10.1364/OE.21.021285 | en |
item.grantfulltext | none | - |
item.fulltext | No Fulltext | - |
Appears in Collections: | EEE Journal Articles |
SCOPUSTM
Citations
20
5
Updated on Jul 8, 2022
PublonsTM
Citations
20
6
Updated on Jul 8, 2022
Page view(s) 10
659
Updated on Aug 14, 2022
Google ScholarTM
Check
Altmetric
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.