A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion

Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/101457

Title:	A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion
Authors:	Tang, Howard Low, Joshua Yung Lih Low, Jeremy Yung Shern Siek, Liter Jong, Ching Chuen Chang, Chip Hong
Keywords:	DRNTU::Engineering::Electrical and electronic engineering
Issue Date:	2012
Source:	Tang, H., Low, J. Y. L., Low, J. Y. S., Siek, L., Jong, C. C., & Chang, C. H. (2012). A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion. 2012 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 272-275.
Conference:	IEEE Asia Pacific Conference on Circuits and Systems (2012 : Kaohsiung, Taiwan)
Abstract:	This paper presents a new 16-bit analog-to-residue converter (ARC) for a three moduli set {26-1, 26, 26+1} RNS with a dynamic range of 18 bits. Based on dual-slope integrating principle, direct conversion from analog to residue representation is achieved with only three modulo counters after the voltage sensing circuits. By eliminating the costly binary-to-residue converter, the proposed ARC saves 81.6% of area in comparison with the conventional two-stage architecture consisting of an integrating ADC and a RNS forward converter.
URI:	https://hdl.handle.net/10356/101457 http://hdl.handle.net/10220/16335
DOI:	10.1109/APCCAS.2012.6419024
Schools:	School of Electrical and Electronic Engineering
Fulltext Permission:	none
Fulltext Availability:	No Fulltext
Appears in Collections:	EEE Conference Papers

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