Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/101669
Title: A low-power single-phase clock multiband flexible divider
Authors: Manthena, Vamshi Krishna
Do, Manh Anh
Boon, Chirn Chye
Yeo, Kiat Seng
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2012
Source: Manthena, V. K., Do, M. A., Boon, C. C., & Yeo, K. S. (2012). A low-power single-phase clock multiband flexible divider. IEEE transactions on very large scale integration (VLSI) systems, 20(2), 376-380.
Series/Report no.: IEEE transactions on very large scale integration (VLSI) systems
Abstract: In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zigbee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers is proposed based on pulse-swallow topology and is implemented using a 0.18-μm CMOS technology. The multiband divider consists of a proposed wideband multimodulus 32/33/47/48 prescaler and an improved bit-cell for swallow (S) counter and can divide the frequencies in the three bands of 2.4-2.484 GHz, 5.15-5.35 GHz, and 5.725-5.825 GHz with a resolution selectable from 1 to 25 MHz. The proposed multiband flexible divider is silicon verified and consumes power of 0.96 and 2.2 mW in 2.4- and 5-GHz bands, respectively, when operated at 1.8-V power supply.
URI: https://hdl.handle.net/10356/101669
http://hdl.handle.net/10220/16540
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2010.2100052
Rights: © 2011 IEEE
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Journal Articles

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