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Title: A unified {2n−1, 2n, 2n+1} RNS scaler with dual scaling constants
Authors: Low, Jeremy Yung Shern
Tay, Thian Fatt
Chang, Chip Hong
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2012
Source: Low, J. Y. S., Tay, T. F., & Chang, C. H. (2012). A unified {2n−1, 2n, 2n+1} RNS scaler with dual scaling constants. 2012 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp.296-299.
Abstract: Scaling is often used to prevent overflow in digital signal processing (DSP). Unfortunately, scaling in residue number system (RNS) consumes significant hardware area and delay. The problem is worsened when more than one scaling factors are needed. Applications in which the computation results fall into two distinct dynamic ranges could benefit from having two scaling factors for better trade-off between precision and hardware savings. This paper presents a new unified architecture for scaling an integer in the three-moduli set {2n-1, 2n, 2n+1} RNS by two different scaling factors, 2n(2n+1) and 2n. The unified architecture has hardware complexity approximating the most compact adder-based RNS scaler for a single scaling constant of 2n. Our analysis shows that the proposed dual scaler design is not only several orders of magnitude smaller but also significantly faster than the fastest LUT-based RNS scalers for the same scaling constants.
DOI: 10.1109/APCCAS.2012.6419030
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Conference Papers

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