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https://hdl.handle.net/10356/101771| Title: | Low-power high-speed dual-modulus prescaler for Gb/s applications | Authors: | Wang, Keping Ma, Kaixue Yeo, Kiat Seng |
Keywords: | DRNTU::Engineering::Electrical and electronic engineering | Issue Date: | 2012 | Source: | Wang, K., Ma, K., & Yeo, K. S. (2012). Low-power high-speed dual-modulus prescaler for Gb/s applications. 2012 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp.256-259. | Conference: | IEEE Asia Pacific Conference on Circuits and Systems (2012 : Kaohsiung, Taiwan) | Abstract: | This paper present a low-power 10-GHz divide-by-3/4 prescaler for 60-GHz high data rate short range wireless communication systems. Design techniques utilized to optimize the power consumption are addressed. The critical circuit, current-mode-logic (CML) blocks, are optimized to achieve high speed and low power consumption simultaneously. The prescaler is implemented in a low-cost commercial 0.18-μm SiGe BiCMOS technology. The maximum operating frequency is up to 10 GHz, with 8.6 mW power consumption in 1.8 V supply. The core area is 190 μm×120 μm. | URI: | https://hdl.handle.net/10356/101771 http://hdl.handle.net/10220/16362 |
DOI: | 10.1109/APCCAS.2012.6419020 | Schools: | School of Electrical and Electronic Engineering | Fulltext Permission: | none | Fulltext Availability: | No Fulltext |
| Appears in Collections: | EEE Conference Papers |
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