Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/102585
Title: Design of simultaneous bi-directional transceivers utilizing capacitive coupling for 3DICs in face-to-face configuration
Authors: Aung, Myat Thu Linn
Lim, Eric
Yoshikawa, Takefumi
Kim, Tony Tae-Hyoung
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2012
Source: Aung, M. T. L., Lim, E., Yoshikawa, T., & Kim, T. T. H. (2012). Design of simultaneous bi-directional transceivers utilizing capacitive coupling for 3DICs in face-to-face configuration. IEEE journal on emerging and selected topics in circuits and systems, 2(2), 257-265.
Series/Report no.: IEEE journal on emerging and selected topics in circuits and systems
Abstract: Capacitive-coupling-based simultaneously bi-directional transceivers for chip-to-chip communication in three-dimensional integrated circuits are presented. By employing a 4-level signaling strategy with a novel cascaded capacitor configuration, the proposed transceivers can transmit and receive data simultaneously through a single inter-chip coupling capacitor, and effectively improve the throughput per interconnect. In this work, the proposed cascaded capacitor structure and its signaling strategy are discussed in details and circuit solutions for transceivers are presented. A parasitic shielding technique is employed in the electrode design to improve signal swings without area overheads. A 16μm×20μm electrode provides the voltage margin as large as 195 mV at 1.2 V supply (verified by post-layout simulation) for signal sensing and recovery. The proposed transceivers are designed in a commercial 65-nm complementary metal-oxide-semiconductor technology.
URI: https://hdl.handle.net/10356/102585
http://hdl.handle.net/10220/16384
DOI: 10.1109/JETCAS.2012.2193839
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Journal Articles

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