Please use this identifier to cite or link to this item:
Title: Multifingers capacitances modeling of 65-Nm CMOS transistor by unit cell method
Authors: Agung, Alit Apriyana Anak
Zhang, Yue Ping
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2012
Source: Agung, A. A. A., & Zhang, Y. P. (2012). Multifingers capacitances modeling of 65-Nm CMOS transistor by unit cell method. International Journal of RF and Microwave Computer-Aided Engineering, 22(3), 297-307.
Series/Report no.: International journal of RF and microwave computer-aided engineering
Abstract: The multifingers' parasitic capacitances modeling of 65-nm CMOS transistors for millimeter-wave application is presented. The modeling is based on simulation approach, which is done by building the devices true dimension in high-frequency structure simulator environment. The material properties of the devices as given by the foundry are used during simulation and then full electromagnetic simulations are carried out to extract the Y-parameters of the model. Unit-cell parameters extraction method is carried out in order to save memory and simulation time. In this case, the multifinger transistors are divided into unit-cells and then the parasitic capacitances of the unit-cells are calculated from the extracted Y-parameter. Based on linear scaling, the parasitic capacitance of the multifingers transistor can be obtained with good accuracy (less than 5% error).
DOI: 10.1002/mmce.20576
Rights: © 2012 Wiley Periodicals, Inc.
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Journal Articles

Page view(s) 50

Updated on Feb 3, 2023

Google ScholarTM




Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.