Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/103213
Title: An asynchronous sub-two-step quantizer for continuous-time sigma-delta modulators
Authors: Tan, Xiao Liang
Chan, Pak Kwong
Dasgupta, U.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Issue Date: 2014
Source: Tan, X. L., Chan, P. K., & Dasgupta, U. (2014). An asynchronous sub-two-step quantizer for continuous-time sigma-delta modulators. 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 710-713.
Series/Report no.: 2014 IEEE International Symposium on Circuits and Systems (ISCAS)
Abstract: This paper presents an asynchronous sub-two-step circuit architecture to reduce the complexity and power consumption of internal analog-to-digital converter (quantizer) for Continuous-Time Sigma-Delta Modulator (CTSDM). By using the proposed new circuit topology, only 1/3 of comparators for a 5-bit quantizer design are needed when compared with the conventional flash based counterpart. The proposed quantizer has been implemented and fabricated in a UMC 65-nm CMOS process. The measured results have shown that the quantizer consumes 0.59 mW at an operating frequency of 250 MS/s in a 1.2 V supply and achieves 28.82 dB SNDR (4.5 ENOB) from the output spectrum.
URI: https://hdl.handle.net/10356/103213
http://hdl.handle.net/10220/25740
DOI: 10.1109/ISCAS.2014.6865234
Rights: © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/ISCAS.2014.6865234].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Conference Papers

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