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Title: Design of frequency-interleaved ADC with mismatch compensation
Authors: Qiu, L.
Zheng, Y. J.
Siek, L.
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2014
Source: Qiu, L., Zheng, Y.J., & Siek, L. (2014). Design of frequency-interleaved ADC with mismatch compensation. Electronics Letters, 50(9), 659-661.
Series/Report no.: Electronics letters
Abstract: A frequency-interleaving-based multichannel analogue-to-digitial converter (ADC) with mismatch compensation is presented, which is immune from the time skew problem that exist in the time-interleaved ADC. The channel mismatches, such as bandwidth mismatch, gain mismatch, offset mismatch and filter bank mismatch, are addressed and modelled in the reconstruction optimisation. A prototype of a four-channel 1 GS/s 12 bit frequency-interleaved ADC (FI-ADC) is designed to demonstrate the mismatch compensation. Simulation results show that the mismatches in the FI-ADC can be compensated effectively.
ISSN: 0013-5194
DOI: 10.1049/el.2014.0577
Schools: School of Electrical and Electronic Engineering 
Rights: © 2014 The Institution of Engineering and Technology. This is the author created version of a work that has been peer reviewed and accepted for publication by Electronics Letters, The Institution of Engineering and Technology. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [DOI:].
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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