Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/103234
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dc.contributor.authorQiu, L.en
dc.contributor.authorZheng, Y. J.en
dc.contributor.authorSiek, L.en
dc.date.accessioned2014-06-30T05:22:28Zen
dc.date.accessioned2019-12-06T21:08:04Z-
dc.date.available2014-06-30T05:22:28Zen
dc.date.available2019-12-06T21:08:04Z-
dc.date.copyright2014en
dc.date.issued2014en
dc.identifier.citationQiu, L., Zheng, Y.J., & Siek, L. (2014). Design of frequency-interleaved ADC with mismatch compensation. Electronics Letters, 50(9), 659-661.en
dc.identifier.issn0013-5194en
dc.identifier.urihttps://hdl.handle.net/10356/103234-
dc.description.abstractA frequency-interleaving-based multichannel analogue-to-digitial converter (ADC) with mismatch compensation is presented, which is immune from the time skew problem that exist in the time-interleaved ADC. The channel mismatches, such as bandwidth mismatch, gain mismatch, offset mismatch and filter bank mismatch, are addressed and modelled in the reconstruction optimisation. A prototype of a four-channel 1 GS/s 12 bit frequency-interleaved ADC (FI-ADC) is designed to demonstrate the mismatch compensation. Simulation results show that the mismatches in the FI-ADC can be compensated effectively.en
dc.format.extent2 p.en
dc.language.isoenen
dc.relation.ispartofseriesElectronics lettersen
dc.rights© 2014 The Institution of Engineering and Technology. This is the author created version of a work that has been peer reviewed and accepted for publication by Electronics Letters, The Institution of Engineering and Technology. It incorporates referee’s comments but changes resulting from the publishing process, such as copyediting, structural formatting, may not be reflected in this document. The published version is available at: [DOI:http://dx.doi.org/10.1049/el.2014.0577].en
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen
dc.titleDesign of frequency-interleaved ADC with mismatch compensationen
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.identifier.doi10.1049/el.2014.0577en
dc.description.versionAccepted versionen
item.grantfulltextopen-
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