Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/103596
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dc.contributor.authorLim, Melvin Heng Lien
dc.contributor.authorGoh, Wang Lingen
dc.contributor.authorQin, Zhiliangen
dc.date.accessioned2013-10-25T03:07:42Zen
dc.date.accessioned2019-12-06T21:16:05Z-
dc.date.available2013-10-25T03:07:42Zen
dc.date.available2019-12-06T21:16:05Z-
dc.date.copyright2012en
dc.date.issued2012en
dc.identifier.citationLim, M. H. L., Goh, W. L., & Qin, Z. (2012). A novel FPGA implementation of mirror-paradigm RS-based QC-LDPC decoder for NVM channels. 2012 International Symposium on Intelligent Signal Processing and Communications Systems, 760-765.en
dc.identifier.urihttps://hdl.handle.net/10356/103596-
dc.description.abstractThe scrutiny of the class of Reed-Solomon (RS) based quasi-cyclic (QC) low-density parity-check (LDPC) codes has inspired the authors to propose a memory efficient mirror-paradigm (MP) RS-based QC-LDPC code by exploiting the geometrical properties from the RS-based QC-LDPC nomenclature. Without any loss in performance, the proposed MPRS-based QC-LDPC code delivers discernible memory savings that address the concerns of hefty H-matrices associated to lengthy codewords for non-volatile memory (NVM) applications. Besides, the MPRS-based QC-LDPC codes are not confined to any particular hardware implementation and are compatible with various decoder architectures to complement other optimization schemes.en
dc.language.isoenen
dc.rights© 2012 IEEEen
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen
dc.titleA novel FPGA implementation of mirror-paradigm RS-based QC-LDPC decoder for NVM channelsen
dc.typeConference Paperen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.contributor.conferenceInternational Symposium on Intelligent Signal Processing and Communications Systems (2012 : Taipei, Taiwan)en
dc.identifier.doi10.1109/ISPACS.2012.6473593en
item.fulltextNo Fulltext-
item.grantfulltextnone-
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