Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/103630
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dc.contributor.authorYe, Wen Binen
dc.contributor.authorYu, Ya Junen
dc.date.accessioned2014-12-22T02:14:54Zen
dc.date.accessioned2019-12-06T21:16:41Z-
dc.date.available2014-12-22T02:14:54Zen
dc.date.available2019-12-06T21:16:41Z-
dc.date.copyright2014en
dc.date.issued2014en
dc.identifier.citationYe, W. B. & Yu, Y. J. (2014). Bit-level multiplierless FIR filter optimization incorporating sparse filter technique. IEEE transactions on circuits and systems I : regular papers, 61(11), 3206 - 3215.en
dc.identifier.issn1549-8328en
dc.identifier.urihttps://hdl.handle.net/10356/103630-
dc.identifier.urihttp://hdl.handle.net/10220/24502en
dc.description.abstractMultiplierless FIR filter optimization has been extensively studied in the past decades to minimize the number of adders. A more accurate measurement of the implementation complexity is the number of full adders counted at bit-level. However, the high computational complexity of the optimization at bit-level hinders the technique from practical applications. In this paper, the sparse filter technique is exploited and makes the search space at bit-level significantly reduced. Thus, the bit-level optimization of multiplierless FIR filters for the first time becomes possible. When the sparse filter technique is employed for the multiplierless filter design, the sparsity of the filter is properly controlled so that the feasibility of the bit-level optimization in discrete space is maintained. Thereafter, in the reduced search space, a tree search algorithm is formulated at bit-level, and techniques to estimate the bit level hardware cost and to accelerate the search are presented. Design examples show that the proposed bit-level optimization method generates designs with lower hardware cost and power consumption than that of the best word-level optimization methods, while the design time is still at an acceptable level. The average power savings to 3 recent published techniques are 13.6%, 8.0% and 26.1%, respectively.en
dc.format.extent11 p.en
dc.language.isoenen
dc.relation.ispartofseriesIEEE transactions on circuits and systems I : regular papersen
dc.rights© 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/TCSI.2014.2327287].en
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuitsen
dc.titleBit-level multiplierless FIR filter optimization incorporating sparse filter techniqueen
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.identifier.doihttp://dx.doi.org/10.1109/TCSI.2014.2327287en
dc.description.versionAccepted versionen
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