Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/103747
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dc.contributor.authorKumm, Martinen
dc.contributor.authorZipf, Peteren
dc.contributor.authorFaust, Mathiasen
dc.contributor.authorChang, Chip Hongen
dc.date.accessioned2013-10-25T04:00:35Zen
dc.date.accessioned2019-12-06T21:19:17Z-
dc.date.available2013-10-25T04:00:35Zen
dc.date.available2019-12-06T21:19:17Z-
dc.date.copyright2012en
dc.date.issued2012en
dc.identifier.citationKumm, M., Zipf, P., Faust, M., & Chang, C. H. (2012). Pipelined adder graph optimization for high speed multiple constant multiplication. 2012 IEEE International Symposium on Circuits and Systems, 49-52.en
dc.identifier.urihttps://hdl.handle.net/10356/103747-
dc.description.abstractThis paper addresses the direct optimization of pipelined adder graphs (PAGs) for high speed multiple constant multiplication (MCM). The optimization opportunities are described and a definition of the pipelined multiple constant multiplication (PMCM) problem is given. It is shown that the PMCM problem is a generalization of the MCM problem with limited adder depth (AD). A novel algorithm to solve the PMCM problem heuristically, called RPAG, is presented. RPAG outperforms previous methods which are based on pipelining the solutions of conventional MCM algorithms. A flexible cost evaluation is used which enables the optimization for FPGA or ASIC targets on high or low abstraction levels. Results for both technologies are given and compared with the most recent methods. Even for the special case of limited AD it is shown that RPAG often produces better results compared to the prominent Hcub algorithm with minimal total AD constraint.en
dc.language.isoenen
dc.rights© 2012 IEEE.en
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen
dc.titlePipelined adder graph optimization for high speed multiple constant multiplicationen
dc.typeConference Paperen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.contributor.conferenceIEEE International Symposium on Circuits and Systems (2012 : Seoul, Korea)en
dc.contributor.researchCentre for High Performance Embedded Systemsen
dc.identifier.doi10.1109/ISCAS.2012.6272072en
item.fulltextNo Fulltext-
item.grantfulltextnone-
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