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|Title:||A memory-efficient high-throughput architecture for lifting-based multi-level 2-D DWT||Authors:||Hu, Yusong
Jong, Ching Chuen
|Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic systems::Signal processing||Issue Date:||2013||Source:||Hu, Y., & Jong, C. C. (2013). A memory-efficient high-throughput architecture for lifting-based multi-level 2-D DWT. IEEE transactions on signal processing, 61(20), 4975-4987.||Series/Report no.:||IEEE transactions on signal processing||Abstract:||In this paper, we present a novel memory-efficient high-throughput scalable architecture for multi-level 2-D DWT. We studied the existing DWT architectures and observed that data scanning method has a significant impact on the memory efficiency of DWT architecture. We propose a novel parallel stripe-based scanning method based on the analysis of the dependency graph of the lifting scheme. With the new scanning method for multi-level 2D DWT, a high memory efficient scalable parallel pipelined architecture is developed. The proposed architecture requires no frame memory and a temporal memory of size only $3 N +682$ for the 3-level DWT decomposition with an image of size $N times N$ pixels with 32 pixels processed concurrently. The elimination of frame memory and the small temporal memory lead to significant reduction in overall size. The proposed architecture has a regular structure and achieves 100% hardware utilization. The synthesis results in 90 nm CMOS process show that the proposed architecture achieves a better area-delay product by 60% and higher throughput by 97% when compared to the best existing design for the CDF (Cohen-Daubechies-Favreau) 9/7 2-D DWT.||URI:||https://hdl.handle.net/10356/104036
|ISSN:||1053-587X||DOI:||10.1109/TSP.2013.2274640||Fulltext Permission:||none||Fulltext Availability:||No Fulltext|
|Appears in Collections:||EEE Journal Articles|
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