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Title: A 0.45V 100-channel neural-recording IC with sub-µW/channel consumption in 0.18µm CMOS
Authors: Han, Dong
Zheng, Yuanjin
Rajkumar, Ramamoorthy
Dawe, Gavin
Je, Minkyu
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2013
Source: Han, D., Zheng, Y., Rajkumar, R., Dawe, G., & Je, M. (2013). A 0.45V 100-channel neural-recording IC with sub-µW/channel consumption in 0.18µm CMOS. 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 290 - 291.
Abstract: Conventional neural-recording systems face limitations in simultaneously achieving a good NEF and low power consumption [1-4]. This is because the input amplifier current consumption is dictated by an input-referred noise requirement that determines the system sensitivity, while the supply voltage is determined by a DR requirement at the analog recording chain output that limits the maximum achievable resolution of the A-to-D conversion. In this paper, a power-efficient neural-recording architecture using a DR-folding technique is presented to enable low-voltage operation without compromising the DR performance. The proposed architecture can operate with only half of the typically required supply voltage, which results in about 50% power reduction.
DOI: 10.1109/ISSCC.2013.6487739
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Conference Papers

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