Please use this identifier to cite or link to this item:
https://hdl.handle.net/10356/105356
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Do, Anh Tuan | en |
dc.contributor.author | Yin, Chun | en |
dc.contributor.author | Velayudhan, Kavitha | en |
dc.contributor.author | Lee, Zhao Chuan | en |
dc.contributor.author | Yeo, Kiat Seng | en |
dc.contributor.author | Kim, Tony Tae-Hyoung | en |
dc.date.accessioned | 2014-09-10T01:12:54Z | en |
dc.date.accessioned | 2019-12-06T21:49:50Z | - |
dc.date.available | 2014-09-10T01:12:54Z | en |
dc.date.available | 2019-12-06T21:49:50Z | - |
dc.date.copyright | 2014 | en |
dc.date.issued | 2014 | en |
dc.identifier.citation | Do, A. T., Yin, C., Velayudhan, K., Lee, Z. C., Yeo, K. S., & Kim, T. T. H. (2014). 0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance. IEEE journal of solid-state circuits, 49(7), 1487-1498. | en |
dc.identifier.uri | https://hdl.handle.net/10356/105356 | - |
dc.description.abstract | This work reports a fully parallel match-line (ML) structure with an automated background checking (ABC) scheme. MLs are pre-charged to an intermediate level by a pulsed current source to minimize power. The proposed ABC scheme uses two dummy rows for digitally adjusting the pulse width and the delay of the sense amplifier enable signals of the CAM without disturbing the normal operation. Therefore, it can continuously track the optimum ML swing, making the CAM tolerant to variations. The proposed ABC scheme achieves the power reduction of 5.5× compared with the conventional ML sensing scheme. In addition, multi-V t transistors are used in the CAM cell to reduce the leakage by 15× while improving the ML discharging speed by 2× when compared with the standard-V t devices at 1.2 V, 80 °C. A test chip was prototyped using a standard 65 nm CMOS process. The average energy consumption is 0.77 fJ/bit/search at 1.2 V/500 MHz. | en |
dc.format.extent | 32 p. | en |
dc.language.iso | en | en |
dc.relation.ispartofseries | IEEE journal of solid-state circuits | en |
dc.rights | © 2014 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: [http://dx.doi.org/10.1109/JSSC.2014.2316241]. | en |
dc.subject | DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems | en |
dc.title | 0.77 fJ/bit/search content addressable memory using small match line swing and automated background checking scheme for variation tolerance | en |
dc.type | Journal Article | en |
dc.contributor.school | School of Electrical and Electronic Engineering | en |
dc.identifier.doi | 10.1109/JSSC.2014.2316241 | en |
dc.description.version | Accepted version | en |
item.fulltext | With Fulltext | - |
item.grantfulltext | open | - |
Appears in Collections: | EEE Journal Articles |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
Content Addressable memory.pdf | 1.16 MB | Adobe PDF | View/Open |
SCOPUSTM
Citations
10
38
Updated on Mar 19, 2024
Web of ScienceTM
Citations
10
30
Updated on Oct 28, 2023
Page view(s) 1
1,456
Updated on Mar 28, 2024
Download(s) 5
561
Updated on Mar 28, 2024
Google ScholarTM
Check
Altmetric
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.