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Title: A 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOS
Authors: Yi, Xiang
Boon, Chirn Chye
Liu, Hang
Lin, Jia Fu
Ong, Jian Cheng
Lim, Wei Meng
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2013
Source: Yi, X., Boon, C. C., Liu, H., Lin, J. F., Ong, J. C., & Lim, W. M. (2013). A 57.9-to-68.3GHz 24.6mW frequency synthesizer with in-phase injection-coupled QVCO in 65nm CMOS. 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
Abstract: Under the influence of increasing demand for high-data-rate communication systems such as 60GHz band applications, the requirements of PLLs keep getting higher. In a mm-Wave direct-conversion transceiver, the quadrature LO signal generation is challenging. The conventional techniques to generate quadrature LO signals suffer from many problems. The method of using a divide-by-2 divider after a VCO with double LO frequency is popular in multi-GHz designs, but it is difficult to be realized at mm-Wave frequencies. Employing passive RC complex filters is another way to generate quadrature signals, but high power is required to compensate its loss. The conventional parallel-coupled QVCO seems to be a good choice for mm-Wave application. However, the approach suffers from poor phase noise. This work presents a fully integrated 57.9-to-68.3GHz frequency synthesizer, which employs an in-phase injection-coupled QVCO (IPIC-QVCO) to produce low-phase-noise quadrature signals with low power.
DOI: 10.1109/ISSCC.2013.6487767
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Conference Papers

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