Please use this identifier to cite or link to this item:
https://hdl.handle.net/10356/105701
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Wang, Bing | en |
dc.contributor.author | Lee, Kwang Hong | en |
dc.contributor.author | Wang, Cong | en |
dc.contributor.author | Wang, Yue | en |
dc.contributor.author | Made, Riko I. | en |
dc.contributor.author | Sasangka, Wardhana Aji | en |
dc.contributor.author | Nguyen, Viet Cuong | en |
dc.contributor.author | Lee, Kenneth Eng Kian | en |
dc.contributor.author | Tan, Chuan Seng | en |
dc.contributor.author | Yoon, Soon Fatt | en |
dc.contributor.author | Fitzgerald, Eugene A. | en |
dc.contributor.author | Michel, Jurgen | en |
dc.contributor.editor | Eldada, Louay A. | en |
dc.contributor.editor | Lee, El-Hang | en |
dc.contributor.editor | He, Sailing | en |
dc.date.accessioned | 2019-08-06T05:58:59Z | en |
dc.date.accessioned | 2019-12-06T21:56:07Z | - |
dc.date.available | 2019-08-06T05:58:59Z | en |
dc.date.available | 2019-12-06T21:56:07Z | - |
dc.date.issued | 2017 | en |
dc.identifier.citation | Wang, B., Lee, K. H., Wang, C., Wang, Y., Made, R. I., Sasangka, W. A., . . . Michel, J. (2017). The integration of InGaP LEDs with CMOS on 200 mm silicon wafers. Proceedings of SPIE - Smart Photonic and Optoelectronic Integrated Circuits XIX, 10107, 101070Y-. doi:10.1117/12.2252030 | en |
dc.identifier.uri | https://hdl.handle.net/10356/105701 | - |
dc.description.abstract | The integration of photonics and electronics on a converged silicon CMOS platform is a long pursuit goal for both academe and industry. We have been developing technologies that can integrate III-V compound semiconductors and CMOS circuits on 200 mm silicon wafers. As an example we present our work on the integration of InGaP light-emitting diodes (LEDs) with CMOS. The InGaP LEDs were epitaxially grown on high-quality GaAs and Ge buffers on 200 mm (100) silicon wafers in a MOCVD reactor. Strain engineering was applied to control the wafer bow that is induced by the mismatch of coefficients of thermal expansion between III-V films and silicon substrate. Wafer bonding was used to transfer the foundry-made silicon CMOS wafers to the InGaP LED wafers. Process trenches were opened on the CMOS layer to expose the underneath III-V device layers for LED processing. We show the issues encountered in the 200 mm processing and the methods we have been developing to overcome the problems. | en |
dc.format.extent | 8 p. | en |
dc.language.iso | en | en |
dc.relation.ispartofseries | Proceedings of SPIE - Smart Photonic and Optoelectronic Integrated Circuits XIX | en |
dc.rights | © 2017 SPIE. All rights reserved. This paper was published in Proceedings of SPIE - Smart Photonic and Optoelectronic Integrated Circuits XIX and is made available with permission of SPIE. | en |
dc.subject | Engineering::Electrical and electronic engineering | en |
dc.subject | InGaP LED | en |
dc.subject | CMOS Integration | en |
dc.title | The integration of InGaP LEDs with CMOS on 200 mm silicon wafers | en |
dc.type | Journal Article | en |
dc.contributor.school | School of Electrical and Electronic Engineering | en |
dc.contributor.conference | SPIE OPTO | en |
dc.identifier.doi | 10.1117/12.2252030 | en |
dc.description.version | Published version | en |
item.grantfulltext | open | - |
item.fulltext | With Fulltext | - |
Appears in Collections: | EEE Journal Articles |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
The integration of InGaP LEDs with CMOS on 200 mm Silicon wafer.pdf | 1.16 MB | Adobe PDF | ![]() View/Open |
Page view(s) 50
393
Updated on May 29, 2023
Download(s) 50
73
Updated on May 29, 2023
Google ScholarTM
Check
Altmetric
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.