Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/105826
Title: A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation
Authors: Kim, Tony Tae-Hyoung
Lee, Zhao Chuan
Do, Anh Tuan
Keywords: Bitline Sensing
DRNTU::Engineering::Electrical and electronic engineering
Static Random Access Memory
Issue Date: 2018
Source: Kim, T. T.-H., Lee, Z. C., & Do, A. T. (2018). A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation. Solid-State Electronics, 139, 60-68. doi:10.1016/j.sse.2017.10.002
Series/Report no.: Solid-State Electronics
Abstract: Ultra-low voltage SRAMs are highly sought-after in energy-limited systems such as battery-powered and self-harvested SoCs. However, ultra-low voltage operation diminishes SRAM read bitline (RBL) sensing margin significantly. This paper tackles this issue by presenting a novel 9T cell with data-independent RBL leakage in combination with an RBL boosting technique for enhancing the sensing margin. The proposed technique automatically tracks process, temperature and voltage (PVT) variations for robust sensing margin enhancement. A test chip fabricated in 65 nm CMOS technology shows that the proposed scheme significantly enlarges the sensing margin compared to the conventional bitline sensing scheme. It also achieves the minimum operating voltage of 0.18 V and the minimum energy consumption of 0.92 J/access at 0.4 V.
URI: https://hdl.handle.net/10356/105826
http://hdl.handle.net/10220/48769
ISSN: 0038-1101
DOI: 10.1016/j.sse.2017.10.002
Rights: © 2017 Elsevier Ltd. All rights reserved. This paper was published in Solid-State Electronics and is made available with permission of Elsevier Ltd.
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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