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dc.contributor.authorKim, Tony Tae-Hyoungen
dc.contributor.authorLee, Zhao Chuanen
dc.contributor.authorDo, Anh Tuanen
dc.identifier.citationKim, T. T.-H., Lee, Z. C., & Do, A. T. (2018). A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation. Solid-State Electronics, 139, 60-68. doi:10.1016/j.sse.2017.10.002en
dc.description.abstractUltra-low voltage SRAMs are highly sought-after in energy-limited systems such as battery-powered and self-harvested SoCs. However, ultra-low voltage operation diminishes SRAM read bitline (RBL) sensing margin significantly. This paper tackles this issue by presenting a novel 9T cell with data-independent RBL leakage in combination with an RBL boosting technique for enhancing the sensing margin. The proposed technique automatically tracks process, temperature and voltage (PVT) variations for robust sensing margin enhancement. A test chip fabricated in 65 nm CMOS technology shows that the proposed scheme significantly enlarges the sensing margin compared to the conventional bitline sensing scheme. It also achieves the minimum operating voltage of 0.18 V and the minimum energy consumption of 0.92 J/access at 0.4 V.en
dc.format.extent22 p.en
dc.relation.ispartofseriesSolid-State Electronicsen
dc.rights© 2017 Elsevier Ltd. All rights reserved. This paper was published in Solid-State Electronics and is made available with permission of Elsevier Ltd.en
dc.subjectBitline Sensingen
dc.subjectDRNTU::Engineering::Electrical and electronic engineeringen
dc.subjectStatic Random Access Memoryen
dc.titleA 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operationen
dc.typeJournal Articleen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.description.versionAccepted versionen
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