An area and energy efficient ultra-low voltage level shifter with pass transistor and reduced-swing output buffer in 65-nm CMOS

Abstract

This brief presents an ultra-low voltage level shifter (LS) with fast and energy-efficient voltage conversion from the deep subthreshold region to the superthreshold region. The proposed LS achieves better performance and increased energy efficiency by addressing the reduced swing and the slow fall transition issues in prior arts. A novel reduced-swing buffer design is proposed to attain lower standby power consumption while a pass transistor is used for improving the speed of the fall transition. The proposed LS consists of only 11 transistors occupying 7.45 μm 2 , which obtains the smallest area among the state-of-the-art ultra-low voltage LSs. Measurement results from a test chip fabricated in 65-nm CMOS technology demonstrate that the proposed LS shows the maximum leakage and speed improvements of 16.3× and 2.7× compared to the Wilson current mirror LS. The proposed LS also accomplishes the maximum switching energy reduction of 8.5× and can convert deep subthreshold voltage as low as 100 mV to the superthreshold voltage of 1.2 V.