Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/106084
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dc.contributor.authorLwin, Ne Kyaw Zwaen
dc.contributor.authorSivaramakrishnan, H.en
dc.contributor.authorChong, Kwen-Siongen
dc.contributor.authorLin, Tongen
dc.contributor.authorShu, Weien
dc.contributor.authorChang, Joseph S.en
dc.date.accessioned2019-07-01T02:58:45Zen
dc.date.accessioned2019-12-06T22:04:17Z-
dc.date.available2019-07-01T02:58:45Zen
dc.date.available2019-12-06T22:04:17Z-
dc.date.copyright2018-11-01en
dc.date.issued2018en
dc.identifier.citationLwin, N. K. Z., Sivaramakrishnan, H., Chong, K. S., Lin, T., Shu, W., & Chang, J. S. (2018). Single-event-transient resilient memory for DSP in space applications. 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP). doi:10.1109/ICDSP.2018.8631639en
dc.identifier.urihttps://hdl.handle.net/10356/106084-
dc.description.abstractWe present a radiation-hardened-by-design (RHBD) memory design that mitigates Single-Event-Transients (SETs), Single-Event-Upsets (SEUs) and Dual-Event-Upsets (DEUs), hence significantly enhancing the reliability of digital signal processors (DSPs) for space applications. We achieve these attributes by combining a Triple-Interlocked Cell (TICE) SRAM cell array and a Triple Modular Redundancy (TMR) voter. The TICE SRAM cells therein self-correct SEUs and DEUs. The TMR voter eliminates SETs. Our proposed RHBD TICE SRAM cells integrated with the TMR voter are also hardened by the layout/sizing RHBD practices. By means of the 128×9-bit memory implementation @ 65nm CMOS, we show that our memory design is inherent SEUand DEU-tolerant, and has 94.83% SET reduction and 92.05% Triple-Event-Upset (TEU) reduction when compared to the memory design embodying the 8-transistor (8-T) SRAM cells.en
dc.description.sponsorshipMOE (Min. of Education, S’pore)en
dc.format.extent5 p.en
dc.language.isoenen
dc.rights© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/ICDSP.2018.8631639en
dc.subjectEngineering::Electrical and electronic engineeringen
dc.subjectComputer Architectureen
dc.subjectSRAM Cellsen
dc.titleSingle-event-transient resilient memory for DSP in space applicationsen
dc.typeConference Paperen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.contributor.conference2018 IEEE 23rd International Conference on Digital Signal Processing (DSP)en
dc.identifier.doi10.1109/ICDSP.2018.8631639en
dc.description.versionAccepted versionen
dc.identifier.rims210623en
item.grantfulltextopen-
item.fulltextWith Fulltext-
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