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Title: Single-event-transient resilient memory for DSP in space applications
Authors: Lwin, Ne Kyaw Zwa
Sivaramakrishnan, H.
Chong, Kwen-Siong
Lin, Tong
Shu, Wei
Chang, Joseph S.
Keywords: Engineering::Electrical and electronic engineering
Computer Architecture
SRAM Cells
Issue Date: 2018
Source: Lwin, N. K. Z., Sivaramakrishnan, H., Chong, K. S., Lin, T., Shu, W., & Chang, J. S. (2018). Single-event-transient resilient memory for DSP in space applications. 2018 IEEE 23rd International Conference on Digital Signal Processing (DSP). doi:10.1109/ICDSP.2018.8631639
Abstract: We present a radiation-hardened-by-design (RHBD) memory design that mitigates Single-Event-Transients (SETs), Single-Event-Upsets (SEUs) and Dual-Event-Upsets (DEUs), hence significantly enhancing the reliability of digital signal processors (DSPs) for space applications. We achieve these attributes by combining a Triple-Interlocked Cell (TICE) SRAM cell array and a Triple Modular Redundancy (TMR) voter. The TICE SRAM cells therein self-correct SEUs and DEUs. The TMR voter eliminates SETs. Our proposed RHBD TICE SRAM cells integrated with the TMR voter are also hardened by the layout/sizing RHBD practices. By means of the 128×9-bit memory implementation @ 65nm CMOS, we show that our memory design is inherent SEUand DEU-tolerant, and has 94.83% SET reduction and 92.05% Triple-Event-Upset (TEU) reduction when compared to the memory design embodying the 8-transistor (8-T) SRAM cells.
DOI: 10.1109/ICDSP.2018.8631639
Rights: © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at:
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Conference Papers

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