Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/106111
Title: A comparative study on asynchronous Quasi-Delay-Insensitive templates
Authors: Chang, Kok-Leong
Lin, Tong
Ho, Weng-Geng
Chong, Kwen-Siong
Gwee, Bah Hwee
Chang, Joseph Sylvester
Issue Date: 2012
Source: Chang, K.-L., Lin, T., Ho, W.-G., Chong, K.-S., Gwee, B. H., & Chang, J. S. (2012). A comparative study on asynchronous Quasi-Delay-Insensitive templates. 2012 IEEE International Symposium on Circuits and Systems, 1819-1822.
Abstract: The robustness of asynchronous logic has proved useful in dealing with contemporary problems in CMOS design such as process variations and power management. However, the general cryptic nature of asynchronous logic has stymied the widespread acceptance of this alternate design technique. Fortunately, the semi-custom approach to asynchronous design reduces the tedious handcrafting efforts that are often non-trivial in large system-on-chips (SoCs). However, even with the adoption of this design approach requires careful selection of asynchronous templates that will suit overall system needs. Therefore in this paper, the most eminent Quasi-Delay-Insensitive asynchronous template families reported to date will be presented, and followed by an in-depth comparison of various design FOMs - template area, static/dynamic capacity, cycle time, latency, throughput and Et2. The most aggressive template (EESTFB) can reach a maximum throughput of 3.56Giga items/s on 0.13µm @ 1.2V.
URI: https://hdl.handle.net/10356/106111
http://hdl.handle.net/10220/17938
DOI: 10.1109/ISCAS.2012.6271621
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Conference Papers

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