Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/106112
Full metadata record
DC FieldValueLanguage
dc.contributor.authorHo, Weng-Gengen
dc.contributor.authorChong, Kwen-Siongen
dc.contributor.authorLin, Tongen
dc.contributor.authorGwee, Bah Hweeen
dc.contributor.authorChang, Joseph Sylvesteren
dc.date.accessioned2013-11-29T06:27:51Zen
dc.date.accessioned2019-12-06T22:04:48Z-
dc.date.available2013-11-29T06:27:51Zen
dc.date.available2019-12-06T22:04:48Z-
dc.date.copyright2012en
dc.date.issued2012en
dc.identifier.citationHo, W.-G., Chong, K.-S., Lin, T., Gwee, B. H., & Chang, J. S. (2012). Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic. 2012 IEEE International Symposium on Circuits and Systems, 492-495.en
dc.identifier.urihttps://hdl.handle.net/10356/106112-
dc.description.abstractWe describe an asynchronous-logic (async) 16×16-bit pipelined multiplier based on our proposed Sense Amplifier-Based Pass Transistor Logic (SAPTL) with emphases on high energy-delay efficiency. The multiplier is targeted for an async multi-core System-On-Chip (SOC). This attribute is achieved by simplifying and optimizing the NMOS pass transistor stacks and decision-making C-element, therein to reduce the circuit area overheads and transistor switchings in SAPTL. Based on the simulations (@1V, 65nm CMOS process), the async 16×16-bit pipelined multiplier based on our proposed SAPTL approach features, on average, 31% shorter delay, 21% lower energy/operation achieving a total of 46% lower energy-delay product, and 16% lesser number of transistors when compared to the reported SAPTL approaches.en
dc.language.isoenen
dc.subjectDRNTU::Engineering::Electrical and electronic engineering::Electronic circuitsen
dc.titleEnergy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logicen
dc.typeConference Paperen
dc.contributor.schoolSchool of Electrical and Electronic Engineeringen
dc.contributor.conferenceIEEE International Symposium on Circuits and Systems (2012 : Seoul, Korea)en
dc.contributor.researchTemasek Laboratoriesen
dc.identifier.doi10.1109/ISCAS.2012.6272073en
item.fulltextNo Fulltext-
item.grantfulltextnone-
Appears in Collections:EEE Conference Papers

SCOPUSTM   
Citations 20

2
Updated on Mar 4, 2021

Page view(s) 20

537
Updated on May 23, 2022

Google ScholarTM

Check

Altmetric


Plumx

Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.