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|Title:||An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability||Authors:||Chen, Junchao
Gwee, Bah Hwee
Chang, Joseph Sylvester
|Keywords:||DRNTU::Engineering::Electrical and electronic engineering||Issue Date:||2012||Source:||Chen, J., Chong, K.-S., Gwee, B. H., & Chang, J. S. (2012). An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability. 2012 IEEE International Symposium on Circuits and Systems (ISCAS), 1835-1838.||Abstract:||We propose a dynamic voltage scalable SRAM capable of efficient bit-interleaving in column to tolerate multiple-bits soft error when integrated with error correction codes (ECC). First, a 10T SRAM bitcell is proposed. It activates only intended bitcells so that stability problem of half-selected bitcells is completely eliminated and the power dissipation in half-selected columns is significantly reduced. Second, a configurable DVS scheme is employed to enable the bitcell to operate like differential 8T during super-threshold region which results in faster operation. The proposed SRAM can operate up to 1.2GHz at 1.2V using 65nm CMOS process. Third, a segmented column multiplex with low overhead is proposed, which greatly reduces the power dissipation due to the column control signals. Consequently, the write and read power dissipations are reduced by up to 40% and 67% respectively. Forth, a hierarchical read bitline is used to reduce the read bitline discharge delay variation due to local and global process variation in subthreshold region, which is a major portion of memory access time. Based on our simulation results, the worst case read bitline discharge delay is reduced by more than 12× at VDD of 0.3V.||URI:||https://hdl.handle.net/10356/106455
|DOI:||10.1109/ISCAS.2012.6271625||Fulltext Permission:||none||Fulltext Availability:||No Fulltext|
|Appears in Collections:||EEE Conference Papers|
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