Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/106483
Title: A fast and compact circuit for integer square root computation based on Mitchell logarithmic method
Authors: Low, Joshua Yung Lih
Jong, Ching Chuen
Low, Jeremy Yung Shern
Tay, Thian Fatt
Chang, Chip Hong
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2012
Source: Low, J. Y. L., Jong, C. C., Low, J. Y. S., Tay, T. F., & Chang, C. H. (2012). A fast and compact circuit for integer square root computation based on Mitchell logarithmic method. 2012 IEEE International Symposium on Circuits and Systems(ISCAS), 1235-1238.
Abstract: A novel non-iterative circuit for computing integer square root based on logarithm is proposed in the paper. Mitchell's methods are used for the logarithmic and antilogarithmic conversions. The proposed method merges two conversion stages into a single one to achieve better accuracy with a compact architecture. Hence, the circuit size and latency are reduced. Compared to an existing design based on the modified Dijkstra algorithm used in a coherent receiver, the proposed design is either 8 times smaller or 9 times faster for 16-bit integer input.
URI: https://hdl.handle.net/10356/106483
http://hdl.handle.net/10220/17744
DOI: 10.1109/ISCAS.2012.6271459
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Conference Papers

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