Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/106812
Title: A discrete artificial bee colony algorithm for the no-idle permutation flowshop scheduling problem with the total tardiness criterion
Authors: Tasgetiren, M. Fatih.
Pan, Quan-Ke.
Suganthan, P. N.
Oner, Adalet.
Keywords: DRNTU::Engineering::Electrical and electronic engineering
Issue Date: 2013
Source: Tasgetiren, M. F., Pan, Q.-K., Suganthan, P.,& Oner, A. (2013). A discrete artificial bee colony algorithm for the no-idle permutation flowshop scheduling problem with the total tardiness criterion. Applied Mathematical Modelling, 37(10-11), 6758-6779.
Series/Report no.: Applied mathematical modelling
Abstract: In this paper, we present a discrete artificial bee colony algorithm to solve the no-idle permutation flowshop scheduling problem with the total tardiness criterion. The no-idle permutation flowshop problem is a variant of the well-known permutation flowshop scheduling problem where idle time is not allowed on machines. In other words, the start time of processing the first job on a given machine must be delayed in order to satisfy the no-idle constraint. The paper presents the following contributions: First of all, a discrete artificial bee colony algorithm is presented to solve the problem on hand first time in the literature. Secondly, some novel methods of calculating the total tardiness from makespan are introduced for the no-idle permutation flowshop scheduling problem. Finally, the main contribution of the paper is due to the fact that a novel speed-up method for the insertion neighborhood is developed for the total tardiness criterion. The performance of the discrete artificial bee colony algorithm is evaluated against a traditional genetic algorithm. The computational results show its highly competitive performance when compared to the genetic algorithm. Ultimately, we provide the best known solutions for the total tardiness criterion with different due date tightness levels for the first time in the literature for the Taillard’s benchmark suit.
URI: https://hdl.handle.net/10356/106812
http://hdl.handle.net/10220/16643
ISSN: 0307-904X
DOI: 10.1016/j.apm.2013.02.011
Schools: School of Electrical and Electronic Engineering 
Fulltext Permission: none
Fulltext Availability: No Fulltext
Appears in Collections:EEE Journal Articles

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