Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/107090
Title: Bitwise partial-sum : a new tool for integral analysis against ARX designs
Authors: Sasaki, Yu
Wang, Lei
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems
DRNTU::Engineering::Computer science and engineering
Issue Date: 2015
Source: Sasaki, Y., & Wang, L. (2015). Bitwise partial-sum : a new tool for integral analysis against ARX designs. IEICE transactions on fundamentals of electronics, communications and computer sciences, E98.A(1), 49-60.
Series/Report no.: IEICE transactions on fundamentals of electronics, communications and computer sciences
Abstract: In this paper, we present a new cryptanalytic tool that can reduce the complexity of integral analysis against Addition-Rotation-XOR (ARX) based designs. Our technique is based on the partial-sum technique proposed by Ferguson et al. at FSE 2000, which guesses subkeys byte to byte in turn, and the data to be analyzed is compressed for each key guess. In this paper, the technique is extended to ARX based designs. Subkeys are guessed bit by bit, and the data is compressed with respect to the value of the guessed bit position and carry values to the next bit position. We call the technique bitwise partial-sum. We demonstrate this technique by applying it to reduced-round versions of HIGHT, which is one of the ISO standard 64-bit block ciphers. Another contribution of this paper is an independent improvement specific to HIGHT. By exploiting linear computations inside the round function, the number of guessed bits during the key recovery phase can be greatly reduced. Together with the bitwise partial-sum, the integral analysis on HIGHT is extended from previous 22 rounds to 26 rounds, while full HIGHT consists of 32 rounds.
URI: https://hdl.handle.net/10356/107090
http://hdl.handle.net/10220/25348
DOI: 10.1587/transfun.E98.A.49
Rights: © 2015 The Institute of Electronics, Information and Communication Engineers. This paper was published in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences and is made available as an electronic reprint (preprint) with permission of The Institute of Electronics, Information and Communication Engineers. The paper can be found at the following official DOI: [http://dx.doi.org/10.1587/transfun.E98.A.49].  One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper is prohibited and is subject to penalties under law.
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:SPMS Journal Articles

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