SRAM devices and circuits optimization toward energy efficiency in multi-Vth CMOS

Abstract

Minimum-energy-driven circuit design is highly required in numerous emerging applications such as mobile electronics, wireless sensor nodes, implantable biomedical devices, etc. Due to high computing capability requirements in such applications, SRAMs play a critical role in energy consumption. This paper presents SRAM energy analysis utilizing multi-threshold (multi-Vth) voltage devices and various circuit techniques for power reduction and performance improvement, and suggests optimal device combinations for energy efficiency improvement. In general, higher-Vth devices are preferred in the cross-coupled latches and the write access transistors for reducing leakage current while lower-Vth devices are desired in the read port for implementing higher performance. However, excessively raised Vth in the write paths, i.e. the cross-coupled latches and the write access transistors, leads to slower write speed than read, quickly nullifying improved energy efficiency. In this work, the energy efficiency improvement of 6.24× is achieved only through an optimal device combination in a commercial 65 nm CMOS technology. Employing power reduction and performance boosting techniques together with the optimal device combination enhances the energy efficiency further up to 33×.