Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/107594
Title: A 16-mW 1-GS/s with 49.6-dB SNDR TI-SAR ADC for software-defined radio in 65-nm CMOS
Authors: Qiu, Lei
Tang, Kai
Zheng, Yuanjin
Siek, Liter
Zhu, Yan
U, Seng-Pan
Keywords: Engineering::Electrical and electronic engineering
Digital Background Calibration
Subradix-2
Issue Date: 2017
Source: Qiu, L., Tang, K., Zheng, Y., Siek, L., Zhu, Y., & U, S.-P. (2018). A 16-mW 1-GS/s with 49.6-dB SNDR TI-SAR ADC for software-defined radio in 65-nm CMOS. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(3), 572-583. doi:10.1109/TVLSI.2017.2771811
Series/Report no.: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Abstract: This paper presents a 10-bit 1-GS/s four-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). To suppress the time skew, the full rate master clock-based sampling technique is adopted. The effect of sampling switch mismatches on time skew is addressed. The measured time skew spurs caused by the sampling switch mismatches are around -52 to -55 dB at Nyquist input. Then, a tap-interpolating fractional delay filters-based digital background time skew calibration technique is proposed. Also, a full analysis of the effects of the various parameters on the time skew generated spur levels is presented, which indicates that the time skew error level is related to the length of calibration filters, calibration range, and bandwidth penalty. The subchannel ADC exploits a 250-MS/s SAR ADC with a low-cost high-speed subradix-2 searching technique. The reference interference of nonbinary TI ADCs is discussed and tolerated by the subradix-2 searching scheme. The proposed adders-based encoding circuit is optimized with lower propagation delay to meet high-speed requirements. The prototype was fabricated in a 65-nm CMOS technology. The measurement results show that the ADC achieves a signal-to-noise-plus-distortion ratio of 49.6 dB with a power of 15.95 mW and a figure of merit of 63 fJ/conversion step when operating at 1-GS/s and 458.1-MHz Nyquist input. The ADC core achieves an area of 0.158 mm2.
URI: https://hdl.handle.net/10356/107594
http://hdl.handle.net/10220/50344
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2017.2771811
Rights: © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TVLSI.2017.2771811.
Fulltext Permission: open
Fulltext Availability: With Fulltext
Appears in Collections:EEE Journal Articles

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