Please use this identifier to cite or link to this item:
|Title:||Low-voltage GHz-range frequency synthesizer||Authors:||Sun, Yuan.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Electronic apparatus and materials||Issue Date:||2008||Source:||Sun, Y. (2008). Low-voltage GHz-range frequency synthesizer. Master’s thesis, Nanyang Technological University, Singapore.||Abstract:||The design of a fully-integrated low-noise frequency synthesizer with low supply voltage is one of the greatest challenges in integrating an RF CMOS transceiver on a single-chip. The trend towards low-cost system-on-chip solutions has resulted in an increasingly noisy environment which perturbs the operations of frequency synthesizers. Large reference spurs will mix with the signals from adjacent channels and hence degrade the SNR and other performances in a wireless transceiver. The problem becomes more severe when the power supply is scaled down along with the scaling of CMOS technology. Therefore, frequency synthesizer design with low reference spurs and low noise is becoming very crucial. This thesis describes design techniques for reducing reference spurs while maintaining fast settling time, through improvements in system architectures as well as the design of charge pump circuit. A spur-reduction technique, which incorporates a high-performance charge pump design with an adaptive PLL architecture, is proposed. The proposed PLL architecture smoothly adapts the loop parameters according to different operating modes, so as to reduce the loop bandwidth in the locked state to further attenuate the reference spurs. The proposed architecture allows the loop filter components to be integrated on chip with a reasonable chip area. Charge pump is the dominant building block causing reference spurs in the output spectrum of PLLs due to non-ideal effects such as current mismatch, leakage current, charge sharing and timing mismatch. The proposed charge pump circuit improves current matching in a wide output range by applying a replica biasing technique with an improved feedback structure that provides stable operation. The percentage current mismatch for the output range from 0.1 V to 1.1 V under a supply voltage of 1.2 V is less than ± 0.5%. By employing differential current-steering switches with one side connected to a DC reference voltage, this charge pump circuit also minimizes feed-through of the input pulses, charge sharing effect and timing mismatch of input clocks. To verify the proposed spur-reduction techniques, a fully-integrated frequency synthesizer is designed for 5-GHz WLAN applications using a 0.18-µm CMOS process with a supply voltage of 1.2 V. To accelerate the design process and shorten the simulation time, behavioral models represented in the Verilog-AMS language have been developed to facilitate a hierarchical design approach which comprises a top-down design process followed by a bottom-up verification process. Design considerations and techniques required for each building block, especially low-voltage design techniques are described in details. Post-layout simulation shows that the synthesizer, operating with a supply voltage of 1.2 V in a 0.18-µm CMOS process, is able to achieve a low reference spur level of -60 dBc and fast settling time of less than 30 µs for a frequency jump of 220 MHz from 5.14 GHz to 5.36 GHz. The total chip area is about 1.1 mm by 1.1 mm including the pad frame.||URI:||http://hdl.handle.net/10356/13125||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.