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|Title:||Multi-step dynamic reference analog-to-digital converter||Authors:||Li, Danping.||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Power electronics||Issue Date:||2008||Source:||Li, D. (2008). Multi-step dynamic reference analog-to-digital converter. Master’s thesis, Nanyang Technological University, Singapore.||Abstract:||The thesis presents the research work on high-speed analog-to-digital converter (ADC), with a design specification of 8 bits of resolution under static operating condition and an effective number of bits (ENOB) of 7 bits at 100 MSample/s. A group of novel Multi-Step Dynamic Reference topologies is proposed in this work, which includes a Two-Step design and a Pipelined one. These converters have built-in digital-to-analog converters (DAC) implemented in the feedforward path to establish the reference voltages dynamically. High-speed conversion is achieved with the same number of comparators as the intended number of bit resolutions. The built-in DACs are realized using simple current steering circuits and R-2R resistor networks. Several techniques such as auto zero, two-step operation, and pipelining are used to achieve the high-speed high-accuracy performance. The Two-Step Dynamic Reference design can achieve a conversion rate of one sample/clock. Compared with the conventional two-step ADC, it does not need to generate residue voltage for the operation of fine stage. The Pipelined design can achieve even higher speed at the expense of more S/H amplifiers and longer latency than the Two-Step one. Residue voltage production is also eliminated, which is a performance limitation in conventional Pipelined ADC. The two proposed topologies use the same basic building blocks. The high-speed comparator is designed using auto-zero technique to realize high accuracy. The effect of channel charge injection is also eliminated by employing proper clock scheme. The sample-and-hold amplifier uses two pair of feedback capacitors, and the interleaving technique is not used for holding the output for a full clock cycle. Folded-cascode structure with gain boosting is utilized for the op-amp to achieve high speed and high accuracy. The R-2R resistor network and current steering circuit employ feedback amplifier to establish accurate reference voltages. The clock generator and bias circuit are also properly designed. An 8-bit Two-Step Dynamic Reference ADC and an 8-bit Pipelined Dynamic Reference ADC are both implemented using the 0.18μm 1P6M CMOS process. The layout of the Pipelined design has also been done. The pre-layout simulation shows that the Two-Step design has a Differential Nonlinearity (DNL) of 0.36LSB and an Integral Nonlinearity (INL) of 0.58LSB; the Signal-to-Noise-and-Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFDR) are 41.13dB and 53.62dB when the input frequency is 20MHz. The post-layout simulation has been carried out for the Pipelined design. It has a DNL of 0.12LSB and an INL of 0.25LSB. The dynamic performance indicates a SNDR of 41.93dB and a SFDR of 56.03dB when the input frequency is 24MHz. The evaluation of SNDR and SFDR with respect to the sampling frequency variation and the input frequency variation were also characterized. The Pipelined Dynamic Reference ADC implemented in this work achieves a comparable performance as the state-of-the-art high speed ADC designs in literature.||URI:||http://hdl.handle.net/10356/13139||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
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