Please use this identifier to cite or link to this item:
|Title:||Scalable and configurable array architectures for matrix computation||Authors:||Luo, Jianwen||Keywords:||DRNTU::Engineering::Electrical and electronic engineering::Computer hardware, software and systems||Issue Date:||2008||Source:||Luo, J. (2008). Scalable and configurable array architectures for matrix computation. Doctoral thesis, Nanyang Technological University, Singapore.||Abstract:||Modern digital signal processing and communications often involve computationally demanding algorithms that deal with large and complex matrix problems such as matrix multiplication and matrix inversion. These computations are commonly demanded in many scientific and engineering applications such as radar signal processing, control algorithms, image and video processing, etc. The matrix algorithms are usually computation and memory intensive. The traditional solutions with digital signal processors or general purpose processors are slow in processing speed and can hardly meet the ever increasing real time processing requirements. An alternative solution to the complex matrix problems is to use hardware accelerators implemented with application specific integrated circuits (ASICs) or reconfigurable hardware such as FPGA devices. The FPGA devices have drawn considerable attention recently due to its reconfigurability feature. With the hardware solutions, data can be processed concurrently in either pipelined or systolic arrays to increase processing speed. The adaptability of the design to different applications or different problem sizes is another important issue to be considered. With the reconfigurability design concept, the same piece of hardware design can be reused for different applications without requiring redesign. To utilize this type of reconfigurable hardware, new design methodology needs to be developed. The new methodology should facilitate short design cycle and promote reusability and reconfigurability. This thesis focuses on studying and exploring the scalable and reconfigurable array architectures for matrix computation, specifically, the highly challenging matrix multiplication and matrix inversion. Several array architectures for matrix multiplication and matrix inversion are proposed, developed and documented here. These architectures have the features of scalable, parameterizable, configurable and efficient in computation speed. A reconfigurable array processor for matrix multiplication is proposed and developed to save both the hardware cost and processing time. The array processor is very versatile and can be configured as a parallel structure, a systolic array or a uniprocessor. The design and implementation of the proposed matrix multiplier, together with its performance in terms of speed and size, are presented in the thesis. A reconfigurable array processor for matrix inversion is proposed and developed to tackle the matrix inversion in two steps. In the first step, the matrix inversion algorithm is divided into two separate segments which can be mapped to the architectures with structural similarity. This allows the computation to be decomposed into and carried out by several simple functional units. By studying the computation sequence, a novel parameterizable Bi-z CORDIC is proposed specially for the functional processing in the matrix inversion. The Bi-z CORDIC takes the advantage of the data processing coherence and eliminates the hardware cost and delay for storing, broadcasting and decomposing the rotation angle values that are usually required. In the second step, two novel mapping methods for mapping efficiently the two-dimensional array onto different linear array architectures are developed. The mapping methods achieve up to 100% processor utilization. With the scalable and reconfigurable matrix processing arrays in hand, different applications can be swapped in and out of a low cost of dynamically reconfigurable computing platforms. A study is carried out on dynamical and partial reconfiguration (DPR). A DPR platform is proposed and developed for matrix computation acceleration. The DPR platform increases the hardware efficiency by dynamically altering the circuits according to the execution requirements without interrupting the operation of the application. With the development of these generically predefined reconfigurable matrix processors and the proposed dynamically reconfigurable computing platform, the feasibility and efficiency of the scalable and reconfigurable array architectures for complex data processing is demonstrated in the thesis.||URI:||http://hdl.handle.net/10356/13299||Fulltext Permission:||open||Fulltext Availability:||With Fulltext|
|Appears in Collections:||EEE Theses|
Items in DR-NTU are protected by copyright, with all rights reserved, unless otherwise indicated.