Please use this identifier to cite or link to this item: https://hdl.handle.net/10356/13309
Title: Research on CMOS latchup in quarter micron technology
Authors: Leong, Kam Chew.
Keywords: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
Issue Date: 1998
Abstract: This research work focuses on exploring the process techniques used to improve latchup immunity especially for 0.25 urn CMOS devices and investigating the behaviour of the parasitic bipolar transistors as the n+/p+ spacing is scaled to the sub-0.25 pm regime.
URI: http://hdl.handle.net/10356/13309
Fulltext Permission: restricted
Fulltext Availability: With Fulltext
Appears in Collections:EEE Theses

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