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https://hdl.handle.net/10356/13309
Title: | Research on CMOS latchup in quarter micron technology | Authors: | Leong, Kam Chew. | Keywords: | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits | Issue Date: | 1998 | Abstract: | This research work focuses on exploring the process techniques used to improve latchup immunity especially for 0.25 urn CMOS devices and investigating the behaviour of the parasitic bipolar transistors as the n+/p+ spacing is scaled to the sub-0.25 pm regime. | URI: | http://hdl.handle.net/10356/13309 | Schools: | School of Electrical and Electronic Engineering | Fulltext Permission: | restricted | Fulltext Availability: | With Fulltext |
Appears in Collections: | EEE Theses |
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File | Description | Size | Format | |
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LEONG_KAM_CHEW_1998.pdf Restricted Access | 9.88 MB | Adobe PDF | View/Open |
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